Prior Art
Conventionally, in a microcomputer with a built-in flash memory as disclosed in Japanese Kokai Publication No. 2001-256213 (“Patent Document 1”), shown in FIG. 14, when value “1” (H level) is set in a control bit of FTEST select register 626 in an erase voltage generating circuit and its peripheral circuits, a switch section 630 connects change terminal 630a and change terminal 630b, and an erase voltage supply end 249 is set to a ground potential. Erase pulse signal ERSM supplied from input terminal 620 is outputted to signal output pad P1 by way of buffer 628, and erase pulse signal ERSM can be externally detected. After input of an erase command, the erase operation is checked to determine if correct or not, by checking if erase pulse signal ERSM is outputted or not outputted from the memory cell subject to be erased to the outside of the microcomputer by way of signal output pads P1 to Pn.
A semiconductor memory IC disclosed in Japanese Kokai Publication No. H5-198200 (“Patent Document 2”) comprises, as shown in FIG. 15, memory cells A1, A2; signal lines L1, L3 for writing data D1, D3 into memory cells A1, A2, respectively; signal lines L5, L6 for reading out memory data D5, D6; signal lines L2, L4 branched from the signal lines L5, L6; selectors S1, S2 for selecting data D1 or D5 and data D3 or D6, respectively; correction circuit C for receiving signals D7, D8 outputted from selectors S1, S2; and signal line L9 for outputting correction circuit signal D9 from correction circuit C. The selectors S1, S2 are set to select input data D1, D3 during a test mode. When normal data D1R is entered on signal line L1, correction circuit C insures that data D9 is the normal data and is outputted without correction. When wrong data DIE is entered on signal line L1, correction circuit C insures that corrected normal data D1R is outputted on signal line L9. In the test mode of the correction circuit C, by directly selecting input data and supplying it from the correction circuit C, data writing or reading in the memory cell is not required, and, thus, the test time is shortened.
In the semiconductor integrated circuit disclosed in Japanese Kokai Publication No. H11-101858 (“Patent Document 3”), as shown in FIG. 16, operation of each address can be checked by comparing the address data of the input address signal and the output address data from address shift register 100.
During a write operation, data signals outputted from external signal input and output pads 103, 104 to bus wirings 143, 144 by way of wirings 123, 124 and logic section 1000 are stored in data shift register 200 through wirings 153, 154. The data signals stored in the data shift register 200 are serially outputted therefrom to pad 107 as write data by way of data output line 127.
During a read operation, a counter 300 is used in place of a memory cell, and the operation is checked. First, the counter 300 is initialized, and predetermined data is preset in the counter 300. Next, a clock signal is entered in the counter 300 from clock pad 108 by way of clock line 128, and the data signal of the data preset in the counter 300 is outputted from the counter 300. The logic section 1000 takes in the data signal outputted from the counter 300, and outputs it to pads 103, 104. When the data of the data signal outputted to the pads 103, 104 and the data set in the counter 300 are equal to each other, the operation of this data line is normal.
Problems to Be Solved by the Invention
In Patent Document 1, without actually erasing by generating erase voltage in the flash memory with a built-in in the microcomputer, erase pulse signal ERSM is outputted to signal output pad P1 by way of buffer 628, and the erase operation is checked to determine whether it is correct or wrong. However, nothing is disclosed about operations other than the erase operation. In the read operation or the write operation, it is required to recognize the address information or data information, or recognize information not used in the erase operation. To check if the address information and data information are recognized correctly or not, actual access to the memory cell may be necessary, and a very long test time may be needed in the case of large storage capacity or longer access time to memory cell may be needed as compared with the circuit operation.
Also in Patent Document 1, to determine whether the erase operation is correct or not, signal output pads P1 to Pn are needed exclusively for the test. Special pads are necessary for test, thereby increasing the chip area.
In Patent Document 2, during the test mode of the correction circuit, input data D1, D3 are selected by selectors S1, S2, and put into the correction circuit. However, nothing is mentioned about confirming whether the internal control operation is normal or not in regards to the command input when writing or reading data, and nothing is disclosed about the confirmation of normal address recognition or internal control in regards to the address information to be entered. When checking the command or address, writing or reading operations of data in the memory cell may be needed, and the test time may not be shortened in such a case.
In Patent Document 3, the operation of the logic section is tested without operating the memory section 3000. However, when testing by write/read operations, exclusive test circuits are necessary for confirming normal address input or normal data input, or generating expectation value data for data output, and the circuit configuration is complicated and the chip size is increased. Moreover, in the exclusive test circuits, routing is different from propagation routing of address and data during normal operation. As a specific operation may occur in testing, the circuit in the memory section cannot be tested.
Further, nothing is disclosed about confirming whether the internal control operation is normal or not in regards to the command input during write/read operations. Defective operation may, thus, not be confirmed in regards to the internal operation when recognizing the command.